Conference paper
Architecting for power management: The IBM® POWER7™ approach
Malcolm Ware, Karthick Rajamani, et al.
HPCA 2010
The past few years have witnessed high-end processors with increasing numbers of cores and larger dies. With limited instruction-level parallelism, chip power constraints, and technology-scaling limitations, designers have embraced multiple cores rather than single-core performance scaling to improve chip throughput. This article examines whether this approach is sustainable by scaling from a state-of-the-art big-chip design point using analytical models. © 2006 IEEE.
Malcolm Ware, Karthick Rajamani, et al.
HPCA 2010
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ICS 2005
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IBM J. Res. Dev