(Invited) cross-layer resilience: Challenges, insights, and the road ahead
- Eric Cheng
- Daniel Mueller-Gritschneder
- et al.
- 2019
- DAC 2019
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17 results for Kevin Skadron
CLEAR: Crosslayer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2016
- DAC 2016
Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
Power-efficient embedded processing with resilience and real-time constraints
- Liang Wang
- Augusto Vega
- et al.
- 2015
- ISLPED 2015
Characterization of transient error tolerance for a class of mobile embedded applications
- Liang Wang
- Ramon Bertran
- et al.
- 2014
- IISWC 2014
The resilience wall: Cross-layer solution strategies
- Subhasish Mitra
- Pradip Bose
- et al.
- 2014
- VLSI-TSA 2014
Impact of thermal constraints on multi-core architectures
- Yingmin Lit
- Benjamin Lee
- et al.
- 2006
- ITherm 2006
CMP design space exploration subject to physical constraints
- Yingmin Li
- Benjamin Lee
- et al.
- 2006
- HPCA 2006
Performance, energy, and thermal considerations for SMT and CMP architectures
- Yingmin Li
- David Brooks
- et al.
- 2005
- HPCA 2005
Power and thermal effects of SRAM vs. latch-mux design styles and clock gating choices
- Yingmin Li
- Mark Hempstead
- et al.
- 2005
- ISLPED 2005