(Invited) cross-layer resilience: Challenges, insights, and the road ahead
- Eric Cheng
- Daniel Mueller-Gritschneder
- et al.
- 2019
- DAC 2019
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17 results for Kevin Skadron
Tolerating soft errors in processor cores using CLEAR (cross-layer exploration for architecting resilience)
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2018
- IEEE TCADIS
Very low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
CLEAR: Crosslayer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2016
- DAC 2016
Near-Memory Data Services
- Babak Falsafi
- Mircea Stan
- et al.
- 2016
- IEEE Micro
Power-efficient embedded processing with resilience and real-time constraints
- Liang Wang
- Augusto Vega
- et al.
- 2015
- ISLPED 2015
Characterization of transient error tolerance for a class of mobile embedded applications
- Liang Wang
- Ramon Bertran
- et al.
- 2014
- IISWC 2014
The resilience wall: Cross-layer solution strategies
- Subhasish Mitra
- Pradip Bose
- et al.
- 2014
- VLSI-TSA 2014
Scaling with design constraints: Predicting the future of big chips
- Wei Huang
- Karthick Rajamani
- et al.
- 2011
- IEEE Micro
Low-power design and temperature management
- Kevin Skadron
- Pradip Bose
- et al.
- 2007
- IEEE Micro