Small silicon memories: Confinement, single-electron, and interface state considerations

Abstract

Memories that utilize single-electron effects are an attempt at combining the discreteness observable in transport of electrons on to very small capacitances (approximately 10-18 F) and into three-dimensionally quantum-confined states, with the reproducibility, architecture and integration of the field-effect devices. We discuss the role size plays in the operation and its variability for such memories. In particular, we discuss the implications of size effects through barriers on speed; through electrostatics on variability, acceptability and reproducibility of properties desired; through random variations and of tunneling on limits in the use of the field-effect, and through interface-states on the time-domain operation. For device properties and their variations, using silicon-on-insulator substrates, silicon and back-insulator thicknesses matter through the linear variations introduced in the electrostatic potential and quadratic variations introduced in the subband energies, the quantum-dots and nano-crystals matter secondarily through the electrostatics and the linear dependence of capacitance on size and the quadratic dependence of the allowed eigen-energies on size. We also discuss the implications of tunneling on time constants of charging of the confined states and in between the source and the drain for the ultimate structure size limit.