Temperature scaling of CMOS circuit power consumption

Abstract

We have analyzed fundamental physical limitations on power consumption of prospective semiconductor digital integrated circuits based on nanoscale silicon MOSFETs, using simple models of these devices and power dissipation. Results show that the temperature dependence of the power is determined by circuit speed requirements. For high-speed operation, both power P and power supply voltage VDD saturate when T is reduced below approximately 100 K. In the low-speed limit, P scales as T2, while VDD drops linearly with T. However, thermal fluctuations may alter this scaling, leading to P ∝ T and VDD ∝ T1/2, at low temperatures and/or large circuit densities. We compare this scaling with that of superconductor RSFQ logic. © 2003 Elsevier Science B.V. All rights reserved.