Michael Moreinis, Arkadiy Morgenshtein, et al.
IEEE Transactions on VLSI Systems
Paper
Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms
Abstract
Editor's note: Hardware-accelerated simulation platforms can significantly reduce the validation time. This article presents an off-platform test generation method and it compares and contrasts it against the on-platform alternative for two state-of-the-art multicore processor designs.
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