Sebastian M. Csutak, Jeremy D. Schaub, et al.
OFC 2002
Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32 nm metal-gate partially depleted SOI process technology, for low-voltage applications. Hardware exhibits a robust operation at 348 MHz and 0.5 V with a read and write power of 3.33 and 1.97 mW, respectively, per 4.5 KB active array when both read ports are accessed at the highest switching activity data pattern. At a 0.6 V supply, an access speed of 1.2 GHz is observed. © 2011 IEEE.
Sebastian M. Csutak, Jeremy D. Schaub, et al.
OFC 2002
Fadi H. Gebara, Jeremy D. Schaub, et al.
VLSI Circuits 2005
Filipp Akopyan, Jun Sawada, et al.
IEEE TCADIS
Christian Baks, Jeremy D. Schaub, et al.
ECTC 2004