The design, fabrication and characterization of 0.15 μm MOS devices

Abstract

The design, fabrication and characterization of a high performance 0.15 μm n-channel and p-channel MOS devices for room temperature operation are described. The design features 5 nm gate oxide, shallow source-drain junction extensions, thin self-aligned titanium silicides, and highly doped wells with low impurity channels for providing low threshold voltages and good turn-off characteristics. A reduced power supply of 1.8V is chosen to optimize device performances without compromising their reliability. n+and p+polysilicon gate electrodes are used to avoid buried channel operation of pMOS device resulting in excellent short channel characteristics. In this paper, measured device characteristics will be discussed. Simulated stage delay of 41ps for for unloaded CMOS inverter using these devices is also presented.