The design of a 4.5GHz CMOS tuned oscillator for clock and data recovery applications

Abstract

This paper describes the design of a tuned harmonic oscillator operating at 4.5GHz and implemented in a copper 0.18um CMOS technology. Harmonic oscillators are becoming increasingly important for the integrated circuit implementation of high frequency voltage controlled oscillators (VCOs) for phase locked loop (PLL) applications. Within CMOS designs, ring oscillator based VCOs have been widely used within PLL systems but since these are relaxation oscillators, the stability of the oscillator is less than that obtained with tuned oscillator using an LC tank circuit. However, until recently, the complete implementation of a harmonic oscillator on an integrated circuit was not practical because of the inductor. Increasing system performance has resulted in clock rates where the inductor value has reduced to a size which can be practically integrated. At the same time, semiconductor processing advances such as copper interconnect have allowed the quality of the integrated inductor to improve to a level where it can be usefully employed within a tuned oscillator. In contrast, it is becoming more difficult to achieve performance improvements with ring oscillator based VCOs as clock rates increase. Improvements in ring oscillator noise performance are requiring higher power levels within the VCO circuit and this is becoming a significant proportion of the PLL ( and chip ) power budget. Harmonic oscillators offer the prospect of a lower power, higher performance VCO than can be achieved with an equivalent ring oscillator design in the same technology. © 2000 The Institution of Electrical Engineers.