A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
- M. Sorna
- T. Beukema
- et al.
- 2005
- ISSCC 2005
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7 results for J.S.B. Mason
A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
- M. Sorna
- T. Beukema
- et al.
- 2005
- ISSCC 2005
Layout techniques for mixed-signal VLSI design
- J.S.B. Mason
- 1999
- IEE Colloquium (Digest)
A 400Mb/s clock and data recovery PLL system in a 0.5UM CMOS asic process
- J.S.B. Mason
- P.J. Murfet
- et al.
- 1999
- IEE Colloquium (Digest)
Transient protection for high speed datacommunication applications
- J.S.B. Mason
- 1998
- IEE Colloquium on Surges, Transients and EMC 1998
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
- Troy Beukema
- Michael Sorna
- et al.
- 2005
- IEEE Journal of Solid-State Circuits
The design of a 4.5GHz CMOS tuned oscillator for clock and data recovery applications
- J.S.B. Mason
- 2000
- IEE Colloquium (Digest)