Low-power memristor-based computing for edge-AI applications
Abhairaj Singh, Sumit Diware, et al.
ISCAS 2021
Capacitance extraction for nanoscale circuits operating at high frequencies plays an important role in accurately modeling postlayout electrical behavior. In this work, for the first time, a layout-independent 3-D technology computer-aided design (TCAD)-based methodology is used to precisely compute front-end-of-the-line (FEOL) and back-end-of-the-line capacitances in SRAM structures using advanced sub-32-nm SOI process assumptions. Results for multicell single-/dual-ported 6T SRAM blocks highlight the need to model FEOL silicon as a semiconductor, incorporating field-carrier interactions (which are completely ignored by field solvers), and the inadequacy of single-cell 3-D TCAD-based capacitance extractions. The 3-D TCAD methodology is applied to an experimental 32-nm SOI process and is in close agreement with measured data, in the presence of FEOL variations. © 2011 IEEE.
Abhairaj Singh, Sumit Diware, et al.
ISCAS 2021
Rajiv V. Joshi, Yuen Chan
ESSCIRC 2005
Pranita Kerber, Rouwaida Kanj, et al.
IEEE Electron Device Letters
David J. Frank, Sudipto Chakraborty, et al.
ISSCC 2022