Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond

Abstract

We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current I OFF down to 10 pA/μm at supply voltage VDD = 1.2 V. NFET/PFET drive current IDSAT = 550/250 μA/tm at IOFF = 100 pA/μm and gate length LG ∼ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre-amorphization implants (PAI), source-side high-damage PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there is no fundamental limit for low leakage application of SOI. © 2007 IEEE.