Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond
- Jin Cai
- Amlan Majumdar
- et al.
- 2007
- IEDM 2007
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18 results for David Dobuzinsky
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
Device Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003
Gate length and performance scaling of undoped-body extremely thin SOI MOSFETs
- Amlan Majumdar
- Xinlin Wang
- et al.
- 2009
- IEEE Electron Device Letters
High-performance undoped-body 8-nm-thin SOI field-effect transistors
- Amlan Majumdar
- Zhibin Ren
- et al.
- 2008
- IEEE Electron Device Letters
Ultra-thin SOI replacement gate CMOS with ALD TaN / high-k gate stack
- B. Doris
- B.P. Linder
- et al.
- 2005
- VLSI-TSA 2005
Structural demonstration of cost effective Isolation Trench fill for sub-110nm vertical trench DRAM and SOC applications
- S.-W. Yang
- W.-S. Liao
- et al.
- 2003
- VLSI-TSA 2003
Cleans for Al vias in a 0.175 μm Dual Damascene Process
- J.P. Gambino
- L. Clevenger
- et al.
- 1999
- IITC 1999
Selection of attenuated phase shift mask compatible contact hole resists for KrF optical lithography
- Zhijian G. Lu
- Yuping Cui
- et al.
- 1999
- SPIE Advances in Resist Technology and Processing 1999
Dielectric anti-reflection coating application in a 0.175 μm dual-damascene process
- G.Y. Lee
- Z.G. Lu
- et al.
- 1998
- IITC 1998