Universal optical multi-drop bus for heterogeneous memory architecture

Abstract

Emerging non-volatile memory device technologies such as flash, FRAM, and PCM are changing the traditional main memory architecture consisting of DRAM. New architecture-level and OS-level refinements with these memory devices have been proposed. However, in practice, modern high performance processors have difficulties in adding attachment points for new memory interfaces, since the number of off-chip pins are limited due to packaging constraints, and many pins are already in use for existing functions such as SMP links, IO links, and power supplies. In this paper, by taking advantage of optics with multi-drop topology, we propose a novel high-bandwidth low-power memory bus architecture that can connect different memory devices at the same time with a single attachment point on the processor chip. The prototyped 75-Gbps optical multi-drop bus platform can organize DDR2 and DDR3 SDRAM DIMMs on the single bus, and can be attached to a processor with industry-standard 12-ch 250-μm-pitch parallel optical fibers. © 2011 Authors.