VHDL as Input for High-Level Synthesis

The authors look at the feasibility of high-level synthesis from a behavioral, sequential description in VHDL. In some cases, the semantics and descriptive power of the language create difficulties for high-level synthesis. In other cases the high-level synthesis framework used imposes limitations. The authors suggest restrictions in the form of rules for overcoming these difficulties. They show that although VHDL semantics were initially defined in terms of simulation, they do not pose any fundamental problems for high-level synthesis. © 1991 IEEE