Layout-aware through-process circuit analysis
Rama Singh, Matt Ziegler, et al.
DTIS 2007
We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Rama Singh, Matt Ziegler, et al.
DTIS 2007
Fook-Luen Heng, Jin-Fuw Lee, et al.
Microlithography 2005
Donald T. Tang, Lin S. Woo
IEEE TC
Zeev Barzilai, Leendert M. Huisman, et al.
IEEE Design and Test of Computers