Algorithm for incremental timing analysis
- Jin-Fuw Lee
- D.T. Tang
- 1995
- DAC 1995
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14 results for Jin-Fuw Lee
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
- Aditya Bansal
- Rama N. Singh
- et al.
- 2009
- ICCAD 2009
Layout-aware through-process circuit analysis
- Rama Singh
- Matt Ziegler
- et al.
- 2007
- DTIS 2007
Toward through-process layout quality metrics
- Fook-Luen Heng
- Jin-Fuw Lee
- et al.
- 2005
- Microlithography 2005
Taming pattern and focus variation in VLSI design
- Fook-Luen Heng
- Puneet Gupta
- et al.
- 2004
- AMM 2004
HIMALAYAS - a hierarchical compaction system with a minimized constraint set
- Jin-Fuw Lee
- D.T. Tang
- 1992
- ICCAD 1992
Layout compaction algorithm with multiple grid constraints
- Jin-Fuw Lee
- 1991
- ICCD 1991
ON VLSI LAYOUT COMPACTION WITH MIXED GRID AND EDGE CONSTRAINTS.
- Jin-Fuw Lee
- D.T. Tang
- 1985
- ICCD 1985
On the signal bounding problem in timing analysis
- Jin-Fuw Lee
- D.L. Ostapko
- et al.
- 2001
- IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
A timing analysis algorithm for circuits with levelsensitive latches
- Jin Fuw Lee
- Donald T. Tang
- et al.
- 1996
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems