Low-energy proton-induced single-event-upsets in 65 nm node, silicon-on-insulator, latches and memory cells
- Kenneth P. Rodbell
- David F. Heidel
- et al.
- 2007
- IEEE TNS
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Latch design techniques for mitigating single event upsets in 65 nm SOI device technology
- A.J. KleinOsowski
- Ethan H. Cannon
- et al.
- 2007
- IEEE TNS
Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells
- David F. Heidel
- Kenneth P. Rodbell
- et al.
- 2006
- IEEE TNS
Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices
- A.J. KleinOsowski
- Phil Oldiges
- et al.
- 2006
- IEEE TNS
FinFET design considerations based on 3-D simulation and analytical modeling
- Gen Pei
- Jakub Kedzierski
- et al.
- 2002
- IEEE Transactions on Electron Devices
Theoretical determination of the temporal and spatial structure of α-particle induced electron-hole pair generation in silicon
- Phil Oldiges
- Robert Dennard
- et al.
- 2000
- IEEE TNS