Soft error rate scaling for emerging SOI technology options

Abstract

The soft error rate in SOI devices is explored. Conventional SOI device soft error rate is compared to high mobility SOI and double gate SOI designs. We develop a theoretical understanding of the susceptibility of SOI devices to a-particle induced soft errors by means of simulations and measurements. Although high mobility devices will decrease soft error rate susceptibility, silicon thinning is shown to have a much larger impact. Double gate devices are shown to improve the soft error rate even further.