A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2018
- VLSI Circuits 2018
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95 results for Thomas Toifl
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- Pier Andrea Francese
- Alessandro Cevrero
- et al.
- 2018
- VLSI Circuits 2018
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
- Lukas Kull
- Danny Luu
- et al.
- 2018
- VLSI Circuits 2018
4×40 Gb/s 2 pJ/bit optical RX with 8ns power-on and CDR-lock time in 14nm CMOS
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2018
- OFC 2018
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
- Gain Kim
- Lukas Kull
- et al.
- 2018
- ISCAS 2018
DDR4 transmitter with ac-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS Technology
- Marcel Kossel
- Christian Menolfi
- et al.
- 2017
- ESSCIRC 2017
Background calibration using noisy reference ADC for a 12b 600MS/s 2×TI SAR ADC in 14nm CMOS FinFET
- Danny Luu
- Lukas Kull
- et al.
- 2017
- ESSCIRC 2017
Adaptive high-speed and ultra-low power optical interconnect for data center communications
- Ronny Henker
- Thomas Toifl
- et al.
- 2017
- ICTON 2017
Analysis and comparative evaluation of stacked-Transistor half-bridge topologies implemented with 14 nm bulk CMOS technology
- Pedro André Martins Bezerra
- R.K. Aljameh
- et al.
- 2017
- COMPEL 2017
A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
- Gautam Gangasani
- John F. Bulzacchelli
- et al.
- 2017
- VLSI Circuits 2017