A NRZ/PAM4 SST TX in 5nm FinFET CMOS with 3-tap FFE and 0.7pJ/b efficiency at 100 Gb/s PAM4
- Marcel Kossel
- Matthias Brandli
- et al.
- 2024
- ESSERC 2024
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.