Publications

This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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30 results for Danny Luu

A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2017
- VLSI Circuits 2017
A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V
- - Elisa Sacco
  - Pier Andrea Francese
  - et al.
- 2017
- VLSI Circuits 2017
A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2017
- VLSI Circuits 2017
Measurement of high-speed ADCs
- - Lukas Kull
  - Danny Luu
- 2017
- CICC 2017
CMOS ADCs Towards 100 GS/s and beyond
- - Lukas Kull
  - Danny Luu
  - et al.
- 2016
- CSICS 2016
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- - Hazar Yueksel
  - Matthias Braendli
  - et al.
- 2016
- ESSCIRC 2016
Design considerations for 50G+ backplane links
- - Thomas Toifl
  - Matthias Braendli
  - et al.
- 2016
- ESSCIRC 2016
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- - Hazar Yueksel
  - Lukas Kull
  - et al.
- 2015
- ESSCIRC 2015
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
- - Hazar Yueksel
  - Matthias Braendli
  - et al.
- 2018
- IEEE TCAS-I
Feedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic
- - Marcel Kossel
  - Matthias Braendli
  - et al.
- 2016
- Electronics Letters