Direct temperature measurement for VLSI circuits and 3-D modeling of self-heating in sub-0.13 μm SOI technologies
- R.V. Joshi
- S.S. Kang
- et al.
- 2005
- VLSID 2005
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136 results for C.T. Chuang
High-density logic techniques with reduced-stack double-gate MOSFETs
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- IEEE International SOI Conference 2005
Dynamic circuit techniques using independently controlled double-gate devices
- J.B. Kuang
- K. Kim
- et al.
- 2005
- IEEE International SOI Conference 2005
Extremely-scaled double-gate CMOS with non-self-aligned back gate
- Keunwoo Kim
- Hussein I. Hanafi
- et al.
- 2005
- VLSI Technology 2005
Novel high-density low-power high-performance double-gate logic techniques
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2004
- IEEE International SOI Conference 2004
Analysis and design of digital CMOS circuits in hybrid SOI-epitaxial technology with different crystal orientations
- Koushik K. Das
- Shih-Hsien Lo
- et al.
- 2004
- IEEE International SOI Conference 2004
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell
- Rajiv V. Joshi
- Saibal Mukhopadhyay
- et al.
- 2004
- ESSCIRC 2004
FinFET SRAM for high-performance low-power applications
- Rajiv V. Joshi
- Richard Q. Williams
- et al.
- 2004
- ESSDERC/ESSCIRC 2004
A novel technique for steady state analysis for VLSI circuits in partially depleted SOI
- R.V. Joshi
- K. Kroell
- et al.
- 2004
- VLSID/Embedded 2004
Analysis and modeling methodology of strained-Si channel-on-insulator (SSOI) MOSFETs
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2003
- VLSI-TSA 2003