1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache
- Joel Silberman
- Naoaki Aoki
- et al.
- 2000
- VLSI Circuits 2000
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31 results for Sang H. Dhong
'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
Custom circuit design as a driver of microprocessor performance
- David H. Allen
- Sang H. Dhong
- et al.
- 2000
- IBM J. Res. Dev
A 1-GHz logic circuit family with sense amplifiers
- O. Takahashi
- Naoaki Aoki
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor
- D. Heidel
- S. Dhong
- et al.
- 1998
- VTS 1998
690ps read-access latency register file for a GHz integer microprocessor
- O. Takahashi
- Joel Silberman
- et al.
- 1998
- ICCD 1998
1.0-GHz single-issue 64-bit PowerPC integer processor
- Joel Silberman
- Naoaki Aoki
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
1 GHz logic circuits with sense amplifiers
- O. Takahashi
- Naoaki Aoki
- et al.
- 1998
- VLSI Circuits 1998
Designing for a gigahertz
- H. Peter Hofstee
- Sang H. Dhong
- et al.
- 1998
- IEEE Micro