O. Takahashi, Joel Silberman, et al.
ICCD 1998
The organization and circuit design of a 1.0-GHz integer processor built in 0.25-μm CMOS technology are presented. A microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented.
O. Takahashi, Joel Silberman, et al.
ICCD 1998
S.D. Posluszny, Naoaki Aoki, et al.
DAC 2000
S.D. Posluszny, Naoaki Aoki, et al.
ICCD 1998
S.D. Posluszny, Naoaki Aoki, et al.
DAC 2000