Conference paper
Design methodology for a 1.0 GHz microprocessor
S.D. Posluszny, Naoaki Aoki, et al.
ICCD 1998
The organization and circuit design of a 1.0-GHz integer processor built in 0.25-μm CMOS technology are presented. A microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented.
S.D. Posluszny, Naoaki Aoki, et al.
ICCD 1998
O. Takahashi, R. Cook, et al.
ICCAD 2005
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VTS 2013
O. Takahashi, Naoaki Aoki, et al.
VLSI Circuits 1998