Plasma-etching processes for ULSI semiconductor circuits
- M. Armacost
- P.D. Hoh
- et al.
- 1999
- IBM J. Res. Dev
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32 results for H.Y. Ng
High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
High-performance 0.08 μm CMOS
- L. Su
- S. Subbanna
- et al.
- 1996
- VLSI Technology 1996
High pressure CVD tungsten-stud formation using RIE cluster processes
- H.Y. Ng
- D.J. Dichauzi
- 1992
- SPIE Microelectronic Processing 1992
Fabrication of Tungsten Local Interconnect for VLSI Bipolar Technology
- N.J. Mazzeo
- J.D. Warnock
- et al.
- 1993
- JES
A novel application of polyimide-W-AI/CU for VLSI interconnect
- R.V. Joshi
- L. Hsu
- et al.
- 1991
- VMIC 1991
Submicron high performance bipolar technology
- T.C. Chen
- J.D. Cressler
- et al.
- 1989
- VLSI Technology 1989
Inverter Performance Of Deep-Submicrometer Mosfet'S
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1988
- IEEE Electron Device Letters
REACTIVE ION ETCHING OF MULTI-LAYER RESIST.
- H.Y. Ng
- D.P. Klaus
- et al.
- 1986
- MRS Fall Meeting 1986