Process induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
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32 results for H.Y. Ng
Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- K.Y. Lim
- V. Chan
- et al.
- 2005
- ESSDERC 2005
Thermally robust dual-work function ALD-MN x MOSFETs using conventional CMOS process flow
- D.-G. Park
- Z. Luo
- et al.
- 2004
- VLSI Technology 2004
Dual work function metal gate CMOS using CVD metal electrodes
- V. Narayanan
- A.C. Callegari
- et al.
- 2004
- VLSI Technology 2004
A 90nm dual damascene hybrid (organic / inorganic) low-k - Copper BEOL integration scheme
- T. Dalton
- A. Cowley
- et al.
- 2003
- ADMETA 2003
0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999
High-performance 0.08 μm CMOS
- L. Su
- S. Subbanna
- et al.
- 1996
- VLSI Technology 1996
High pressure CVD tungsten-stud formation using RIE cluster processes
- H.Y. Ng
- D.J. Dichauzi
- 1992
- SPIE Microelectronic Processing 1992
A novel application of polyimide-W-AI/CU for VLSI interconnect
- R.V. Joshi
- L. Hsu
- et al.
- 1991
- VMIC 1991
Submicron high performance bipolar technology
- T.C. Chen
- J.D. Cressler
- et al.
- 1989
- VLSI Technology 1989