An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors
- Christophe Tretz
- Chen Guo
- et al.
- 2010
- IEEE International SOI Conference 2010
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10 results for Christophe Tretz
Optimal design of nanoscale triple-gate devices
- Meng-Hsueh Chiang
- Tze-Neng Lin
- et al.
- 2006
- IEEE SOI 2006
High-density logic techniques with reduced-stack double-gate MOSFETs
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- IEEE International SOI Conference 2005
Single polysilicon gate high-density logic using independently-controlled double-gate devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- A-SSCC 2005
Novel high-density low-power high-performance double-gate logic techniques
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2004
- IEEE International SOI Conference 2004
Ratioed CMOS: A low power high speed design choice in SOI technologies
- Christophe R. Tretz
- Robert K. Montoye
- et al.
- 2000
- IEEE International SOI Conference 2000
Performance comparison of differential static CMOS circuit topologies in SOI technology
- Christophe R. Tretz
- C.T. Chuang
- et al.
- 1998
- IEEE International SOI Conference 1998
High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2006
- IEEE Transactions on Electron Devices
Novel high-density low-power logic circuit techniques using DG devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- IEEE Transactions on Electron Devices
Metastability of SOI CMOS latches
- Christophe R. Tretz
- C.T. Chuang
- et al.
- 1999
- International Journal of Electronics