B.S. Wu, C.T. Chuang, et al.
IEEE Transactions on Electron Devices
An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbuffered latch. The metastability window, resolution time and time interval between the clock edge and the time tmeta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI specific body-connection topologies. © 1999 Taylor and Francis Group, LLC.
B.S. Wu, C.T. Chuang, et al.
IEEE Transactions on Electron Devices
R.V. Joshi, F. Yee, et al.
IEEE International SOI Conference 2002
R.V. Joshi, S.S. Kang, et al.
AMC 2001
Rajiv V. Joshi, Richard Q. Williams, et al.
ESSDERC/ESSCIRC 2004