B.S. Wu, C.T. Chuang, et al.
IEEE Transactions on Electron Devices
Paper
Metastability of SOI CMOS latches
Abstract
An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbuffered latch. The metastability window, resolution time and time interval between the clock edge and the time tmeta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI specific body-connection topologies. © 1999 Taylor and Francis Group, LLC.
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