Solder Injected through Via for Multi Stacked Wafers
- Akihiro Horibe
- Kuniaki Sueoka
- et al.
- 2016
- ECTC 2016
Publications
Date
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21 results for Keishi Okamoto
Through silicon via process for effective multi-wafer integration
- Akihiro Horibe
- Kuniaki Sueoka
- et al.
- 2015
- ECTC 2015
Thermally enhanced pre-applied underfills for 3D integration
- Akihiro Horibe
- Keishi Okamoto
- et al.
- 2013
- ECTC 2013
No Clean Flux technology for large die flip chip packages
- Akihiro Horibe
- Kang-Wook Lee
- et al.
- 2013
- ECTC 2013
Electromigration analysis of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump
- Yasumitsu Orii
- Kazushige Toriyama
- et al.
- 2011
- ECTC 2011
Effects of in-plane property variations on warpage shapes of organic substrates
- Sayuri Kohara
- Keishi Okamoto
- et al.
- 2019
- EPTC 2019
CFD analysis of molten solder flow behavior and bridging mechanism during solder bump formation
- Risa Miyazawa
- Keishi Okamoto
- et al.
- 2019
- InterPACK 2019
Effects of build-up material properties on warpage dispersion of organic substrates caused by manufacturing variations
- Keishi Okamoto
- Sayuri Kohara
- et al.
- 2017
- InterPACK 2017
The mechanism of the low-k stress reduction in chip assembly by shorter solder bump height
- Keiji Matsumoto
- Keishi Okamoto
- et al.
- 2017
- InterPACK 2017
Advanced interconnect technologies in the era of cognitive computing
- Yasumitsu Orii
- Akihiro Horibe
- et al.
- 2016
- Pan Pacific 2016