Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications
- Guohan Hu
- D. Kim
- et al.
- 2019
- IEDM 2019
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17 results for C. Kothandaraman
Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs
- Guohan Hu
- M. G. Gottwald
- et al.
- 2017
- IEDM 2017
Vertical channel devices enabled by through silicon via (TSV) technologies
- C. Kothandaraman
- Sami Rosenblatt
- et al.
- 2016
- IEDM 2016
3D copper TSV integration, testing and reliability
- Mukta Farooq
- T. Graves-Abe
- et al.
- 2011
- IEDM 2011
The Impact of Self-Heating on Charge Trapping in High-k-Metal-Gate nFETs
- Faraz Khan
- Eduard Cartier
- et al.
- 2016
- IEEE Electron Device Letters
Low-current spin transfer torque MRAM
- Guohan Hu
- J. J. Nowak
- et al.
- 2017
- VLSI-TSA 2017
Low-current Spin Transfer Torque MRAM
- Guohan Hu
- J. J. Nowak
- et al.
- 2017
- VLSI-DAT 2017
Triangular Voltage Sweep (TVS) characterisation for Through-Silicon-Via (TSV) reliability
- C. Kothandaraman
- Stephan A. Cohen
- 2016
- IRPS 2016
Low-current spin transfer torque MRAM
- D.C. Worledge
- A. Annunziata
- et al.
- 2015
- INTERMAG 2015
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
- C. Kothandaraman
- X. Chen
- et al.
- 2015
- IRPS 2015