Competitive and cost effective high-k based 28nm CMOS technology for low power applications
- F. Arnaud
- A. Thean
- et al.
- 2009
- IEDM 2009
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8 results for R. Lindsay
Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- J.-P. Han
- H. Utomo
- et al.
- 2006
- IEDM 2006
Design of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008
Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
- Xiaobin Yuan
- Jae-Eun Park
- et al.
- 2007
- IIRW 2007
A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Gate-induced-drain-leakage current in 45-nm CMOS technology
- Xiaohin Yuan
- Jae-Eun Park
- et al.
- 2008
- IEEE T-DMR