NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Publications
9 results for A. R. Hubbard
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
Material and process improvements towards sub 36nm pitch EUV single exposure
- Karen Petrillo
- Dave Hetzer
- et al.
- 2019
- ANTS 2019
The defect mitigation on EUV stack by track based technology
- Naoki Shibata
- Lior Huli
- et al.
- 2019
- SPIE Advanced Lithography 2019
Track based techniques to improve high-resolution EUV patterning defectivity
- Naoki Shibata
- Lior Huli
- et al.
- 2018
- EUVL 2018
Coater/developer based techniques to improve high-resolution EUV patterning defectivity
- Koichi Hontake
- Lior Huli
- et al.
- 2017
- SPIE Photomask Technology + EUV Lithography 2017
Driving down defect density in composite EUV patterning film stacks
- Luciana Meli
- Karen Petrillo
- et al.
- 2017
- SPIE Advanced Lithography 2017
Essential edge protection techniques for successful multi-wafer stacking
- Joshua Rubin
- Kevin Winstel
- et al.
- 2015
- S3S 2015
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
- K. Cheng
- A. Khakifirooz
- et al.
- 2012
- IEDM 2012