NanoStack Transistor Architecture for CMOS 7A Node and Beyond

NanoStack is a sequential stacking CMOS transistor architecture featuring flexible placement of top and bottom nanosheet channels, thermally stable bottom FET gate stack, thin dielectric bonding and more. We project NanoStack with 4-track base cells to deliver ∼ 50% area scaling, ∼ 50% iso-power performance improvement or ∼ 70% iso-performance power reduction with respect to the 2nm node, fulfilling fundamental requirements for a competitive multi-node CMOS architecture beyond nanosheet. We demonstrate here for the first time a manufacturable sequential integration of multi-channel nanosheet-on-nanosheet NanoStack CMOS featuring ultra-scaled vertical inter-FET isolation.