Full copper wiring in a sub-0.25 μm CMOS ULSI technology
- D. Edelstein
- J. Heidenreich
- et al.
- 1997
- IEDM 1997
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20 results for H.S. Rathore
A DUAL DAMASCENE HARD METAL CAPPED CU AND AL-ALLOY FOR INTERCONNECT WIRING OF ULSI CIRCUITS
- H. Dalai
- R.V. Joshi
- et al.
- 1993
- IEDM 1993
Stress migration reliability of copper interconnect stacked via structures with adjacent copper plates in low k- dielectrics
- D. Nguyen
- Kaushik Chanda
- et al.
- 2005
- VMIC 2005
Electromigration in sub-micron Cu interconnects in low k dielectrics
- B.N. Agarwala
- D. Nguyen
- et al.
- 2005
- ECS Meeting 2005
Electrical and reliability evaluation of Cu/Low-k integration: Exploration of PVD barrier/seed and CVD SiC(N,H) cap depositions
- C.-C. Yang
- D. Edelstein
- et al.
- 2004
- ADMETA 2004
Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology
- D. Edelstein
- C.R. Davis
- et al.
- 2004
- IITC 2004
90 nm SiCOH technology in 300 mm manufacturing
- L. Clevenger
- M. Yoon
- et al.
- 2004
- ADMETA 2004
Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
- D. Edelstein
- H.S. Rathore
- et al.
- 2004
- IRPS 2004
Measurements of effective thermal conductivity for advanced interconnect structures with various composite low-K dielectrics
- F. Chen
- J. Gill
- et al.
- 2004
- IRPS 2004
Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric
- R. Filippi
- J.F. McGrath
- et al.
- 2004
- IRPS 2004