High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Publications
Date
Featured collections
Popular topics
12 results for Huilong Zhu
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
Device Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003
20 nm N + abrupt junction formation in Strained Si/Si 1-xGe x MOS device
- K.L. Lee
- F. Cardone
- et al.
- 2003
- IEDM 2003
Sub-30 nm P+ abrupt junction formation in strained Si/Si1-xGex MOS device
- K.L. Lee
- J.O. Chu
- et al.
- 2002
- IEDM 2002
On the control of short-channel effect for MOSFETs with reverse halo implantation
- Huilong Zhu
- Huicai Zhong
- et al.
- 2007
- IEEE Electron Device Letters
Improving yields of high performance 65 nm chips with sputtering top surface of dual stress liner
- Huilong Zhu
- Daewon Yang
- et al.
- 2007
- VLSI Technology 2007
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Modeling of germanium and antimony diffusion in Si1.xGe x
- Huilong Zhu
- 2004
- ECS Meeting 2004
Sub-30 NM abrupt junction formation in strained silicon/silicon-germanium CMOS device
- K.-L. Lee
- F. Cardone
- et al.
- 2004
- ECS Meeting 2004