Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- VLSI Technology 2006
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90 results for Meikei Ieong
Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006
Critical aspects of layer transfer and alignment tolerances for 3D integration processes
- D.C. La Tulipe
- L.T. Shi
- et al.
- 2006
- GBC 2006
Process induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
High performance FDSOI CMOS technology with metal gate and high-k
- Bruce Doris
- Y.-H. Kim
- et al.
- 2005
- VLSI Technology 2005
Optimization of high κ gate stacks with poly-Si, FUSI and metal electrodes
- R. Jammy
- V. Narayanan
- et al.
- 2005
- ISTC 2005
Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates
- Qiqing Ouyang
- Min Yang
- et al.
- 2005
- VLSI Technology 2005
Mobility and CMOS devices/circuits on sub-10nm (110) ultra thin body SOI
- Huiling Shang
- J. Rubino
- et al.
- 2005
- VLSI Technology 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005
Assembly technology for three dimensional integrated circuits
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- VMIC 2005