High performance transistors featured in an aggressively scaled 45nm bulk CMOS technologyZ. LuoN. Rovedoet al.2007VLSI Technology 2007
Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substratesHaizhou YinZ. Renet al.2006ICSICT 2006
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyondHaoren ZhuangHelen Wanget al.2007ISTC 2007
Critical aspects of layer transfer and alignment tolerances for 3D integration processesD.C. La TulipeL.T. Shiet al.2006GBC 2006
Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate lengthJames PanAnna Topolet al.2006VLSI Technology 2006
Silicon-on-insulator MOSFETs with hybrid crystal orientationsM. YangK.K. Chanet al.2006VLSI Technology 2006
Investigation of FinFET devices for 32nm technologies and beyondH. ShangL. Changet al.2006VLSI Technology 2006
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substratesHaizhou YinZ. Renet al.2006VLSI Technology 2006
Tunable Workfunction for Fully Silicied Gates (FUSI) and Proposed MechanismsY.-H. KimC. Cabral Jr.et al.2006VLSI-TSA 2006