'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
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6 results for Kyung Tek Lee
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
1 GHz leading zero anticipator using independent sign-bit determination logic
- Kyung Tek Lee
- K. Nowka
- 2000
- VLSI Circuits 2000
Critical path identification and delay tests of dynamic circuits
- Kyung Tek Lee
- Jacob A. Abraham
- 1999
- IEEE ITC 1999
Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
1.0-GHz single-issue 64-bit PowerPC integer processor
- Joel Silberman
- Naoaki Aoki
- et al.
- 1998
- IEEE Journal of Solid-State Circuits