SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
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7 results for T. Dyer
Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy
- Yaocheng Liu
- Oleg Gluschenkov
- et al.
- 2007
- VLSI Technology 2007
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007
A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Process induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
A Simplified Hybrid Orientation Technology (SHOT) for high performance CMOS
- B. Doris
- Y. Zhang
- et al.
- 2004
- VLSI Technology 2004