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High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOLW.-H. LeeA. Waiteet al.2005IEDM 2005
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65nm Cu integration and interconnect reliability in low stress K=2.75 SiCOHV. McGahayG. Bonillaet al.2006IITC 2006
PECVD Low-k (∼2.7) dielectric SiCOH film development and integration for 65 nm CMOS devicesK. IdaS. Nguyenet al.2005AMC 2005
BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65nm groundrulesS. LaneM. Fukasawaet al.2005AMC 2005
BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrulesM. FukasawaS. Laneet al.2005IITC 2005
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cellE. LeobandungH. Nayakamaet al.2005VLSI Technology 2005
Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodesT. NogamiS. Laneet al.2005Optics East 2005