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A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technologyS. SankaranS. Araiet al.2006IEDM 2006
65nm Cu integration and interconnect reliability in low stress K=2.75 SiCOHV. McGahayG. Bonillaet al.2006IITC 2006
BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65nm groundrulesS. LaneM. Fukasawaet al.2005AMC 2005
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BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrulesM. FukasawaS. Laneet al.2005IITC 2005
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cellE. LeobandungH. Nayakamaet al.2005VLSI Technology 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOLW.-H. LeeA. Waiteet al.2005IEDM 2005
Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodesT. NogamiS. Laneet al.2005Optics East 2005