3-D silicon integration and silicon packaging technology using silicon through-vias
- John U. Knickerbocker
- Chirag S. Patel
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
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36 results for Chirag S. Patel
Sea-of-Leads MEMS I/O interconnects for low-k IC packaging
- Bing Dang
- Muhannad S. Bakir
- et al.
- 2006
- JMEMS
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2005
- IBM J. Res. Dev
Electrical test strategies for a wafer-level packaging technology
- David C. Keezer
- Chirag S. Patel
- et al.
- 2003
- IEEE Transactions on Electronics Packaging Manufacturing
Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)
- Muhannad S. Bakir
- Hollie A. Reed
- et al.
- 2003
- IEEE Transactions on Electron Devices
Interconnect opportunities for gigascale integration
- James D. Meindl
- Jeffrey A. Davis
- et al.
- 2002
- IBM J. Res. Dev