Die-to-wafer 3D integration technology for high yield and throughput
- Katsuyuki Sakuma
- Paul S. Andry
- et al.
- 2008
- MRS Fall Meeting 2008
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36 results for Chirag S. Patel
3D silicon integration
- J. Knickerbocker
- P. Andry
- et al.
- 2008
- ECTC 2008
300-Gb/s 24-channel bidirectional Si carrier transceiver optochip for board-level interconnects
- Fuad E. Doany
- Clint L. Schow
- et al.
- 2008
- ECTC 2008
50μm pitch Pb-free micro-bumps by C4NP technology
- Bing Dang
- Da-Yuan Shih
- et al.
- 2008
- ECTC 2008
Characterization of stacked die using die-to-wafer integration for high yield and throughput
- K. Sakuma
- P. Andry
- et al.
- 2008
- ECTC 2008
3D chip stacking technology with low-volume lead-free interconnections
- K. Sakuma
- P. Andry
- et al.
- 2007
- ECTC 2007
Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-package
- B. Dang
- S.L. Wright
- et al.
- 2007
- ECTC 2007
CMOS-compatible through silicon vias for 3D process integration
- Cornelia K. Tsang
- Paul S. Andry
- et al.
- 2006
- MRS Fall Meeting 2006
System-on-Package (SOP) technology, characterization and applications
- J. Knickerbocker
- P. Andry
- et al.
- 2006
- ECTC 2006
Characterization of micro-bump C4 interconnects for Si-carrier SOP applications
- S.L. Wright
- R.J. Polastre
- et al.
- 2006
- ECTC 2006