0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
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3 results for T. Kebede
A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007