Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
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5 results for Hari Amanapu
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
CMP: Consideration of stop-on selectivity in advanced node semiconductor manufacturing technology
- Stan Tsai
- Hari Amanapu
- et al.
- 2017
- ECS Meeting 2017 - New Orleans
Annealing and impurity effects in co thin films for MOL Contact and BEOL metallization
- James Kelly
- Vimal Kamineni
- et al.
- 2018
- JES