Jim Adkisson, Marwan H. Khater, et al.
ECS Meeting 2012
This work thoroughly investigates the external parasitic resistance in advanced FinFET technology. The optimization of the parasitic resistance is systematically examined in terms of 1) source/drain epi resistance, 2) contact resistance and 3) middle of line metal stud resistance. Various resistance reduction knobs have been experimentally explored in these three aspects and low contact resistivity of 1× 10 -9 and 7× 10 -10 Ω cm 2 have been demonstrated on transistor level for NFET and PFET. By combining all the parasitic resistance reduction strategies, more than 70% and 60% reductions [1] in external parasitic resistance have been realized on NFET and PFET, respectively.
Jim Adkisson, Marwan H. Khater, et al.
ECS Meeting 2012
Barry P. Linder, A. Dasgupta, et al.
IRPS 2016
Sadanand V. Deshpande, Ahmet Ozcan, et al.
IWJT 2010
X. Yu, Oleg Gluschenkov, et al.
IEDM 2011