Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Publications
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25 results for Mark Raymond
Annealing and impurity effects in co thin films for MOL Contact and BEOL metallization
- James Kelly
- Vimal Kamineni
- et al.
- 2018
- JES
Validity and Application of the TCR Method to MOL contactS
- E. Milosevic
- Vimal Kamineni
- et al.
- 2018
- IITC 2018
Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study
- Nicholas A. Lanzillo
- H. Dixit
- et al.
- 2018
- Journal of Applied Physics
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Extreme-low k porous pSiCOH dielectrics prepared by PECVD
- H. You
- Petra Mennell
- et al.
- 2018
- JVSTB
First-Principles Investigations of TiGe/Ge Interface and Recipes to Reduce the Contact Resistance
- H. Dixit
- Chengyu Niu
- et al.
- 2017
- IEEE T-ED
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
- Zuoguang Liu
- Oleg Gluschenkov
- et al.
- 2017
- VLSI Technology 2017
Middle of line RC performance study at the 7 nm node
- Susan Su Chen Fan
- James H.-C. Chen
- et al.
- 2017
- IITC 2017
Methods to lower the resistivity of ruthenium interconnects at 7 nm node and beyond
- Xunyuan Zhang
- Huai Huang
- et al.
- 2017
- IITC 2017