1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
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12 results for Giuseppe La Rosa
Long Term NBTI Relaxation under AC and DC Biased Stress and Recovery
- Elnatan Mataev
- James Stathis
- et al.
- 2019
- IRPS 2019
Estimating transistor channel temperature using time-resolved and time-integrated NIR emission
- Franco Stellari
- Alan J. Weger
- et al.
- 2018
- IRPS 2018
Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability
- Mukta Farooq
- Giuseppe La Rosa
- et al.
- 2015
- IRPS 2015
Process dependence of AC/DC PBTI in HKMG n-MOSFETs
- Wen Liu
- Giuseppe La Rosa
- et al.
- 2014
- IRPS 2014
A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS
- D.P. Ioannou
- K. Zhao
- et al.
- 2011
- IRPS 2011
Impact of source/drain contact and gate finger spacing on the RF reliability of 45-nm RF nMOSFETs
- Rajan Arora
- Sachin Seth
- et al.
- 2011
- IRPS 2011
Impact of NBTI induced statistical variation to SRAM cell stability
- Giuseppe La Rosa
- Wee Loon Ng
- et al.
- 2006
- IRPS 2006
Is product screen enough to guarantee low failure rate for the customer?
- M.W. Ruprecht
- G. La Rosa
- et al.
- 2001
- IRPS 2001
NBTI-Channel Hot Carrier effects in pMOSFETs in advanced CMOS technologies
- G. La Rosa
- F. Guarin
- et al.
- 1997
- IRPS 1997