Publications

2 results for Aditya Khargonekar

A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- - Peter J. Klim
  - John Barth
  - et al.
- 2009
- IEEE Journal of Solid-State Circuits
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- - Peter Klim
  - John Barth
  - et al.
- 2008
- VLSI Circuits 2008