Conference paper
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
John Barth, Don Plass, et al.
VLSI Circuits 2012
Conference paper
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
Abstract
We present a 1MB cache subsystem that integrates 2GHz embedded DRAM macros, charge pump circuits, a 4Kb one-time-programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5GB/s peak system data-rate. The eDRAM employs a programmable pipeline, achieving a 1.8ns latency. © 2008 IEEE.