Conference paper
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
John Barth, Don Plass, et al.
VLSI Circuits 2012
We present a 1MB cache subsystem that integrates 2GHz embedded DRAM macros, charge pump circuits, a 4Kb one-time-programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5GB/s peak system data-rate. The eDRAM employs a programmable pipeline, achieving a 1.8ns latency. © 2008 IEEE.
John Barth, Don Plass, et al.
VLSI Circuits 2012
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IEEE Journal of Solid-State Circuits
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VLSI Circuits 2008
Nauman Z. Butt, Kevin McStay, et al.
IEDM 2010