A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
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48 results for E. Nowak
A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology
- Rajiv V. Joshi
- Keunwoo Kim
- et al.
- 2007
- VLSID 2007
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Assembly technology for three dimensional integrated circuits
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- VMIC 2005
FinFET SRAM for high-performance low-power applications
- Rajiv V. Joshi
- Richard Q. Williams
- et al.
- 2004
- ESSDERC/ESSCIRC 2004
A Simplified Hybrid Orientation Technology (SHOT) for high performance CMOS
- B. Doris
- Y. Zhang
- et al.
- 2004
- VLSI Technology 2004
Scaling beyond the 65 nm node with FinFET-DGCMOS
- E. Nowak
- T. Ludwig
- et al.
- 2003
- CICC 2003
FinFET Technology for Future Microprocessors
- T. Ludwig
- I. Aller
- et al.
- 2003
- IEEE International SOI Conference 2003
A Fin-type independent-double-gate NFET
- D. Fried
- E. Nowak
- et al.
- 2003
- Device Research Conference 2003