Intelligent interleaving of scenarios: A novel approach to system level test generation
- Shady Copty
- Itai Jaeger
- et al.
- 2007
- DAC 2007
Publications
Date
Featured collections
Popular topics
7 results for Michael Vinov
VLIW - A case study of parallelism verification
- Allon Adir
- Yaron Arbetman
- et al.
- 2005
- DAC 2005
Industrial experience with test generation languages for processor verification
- Michael Behm
- John Ludden
- et al.
- 2004
- DAC 2004
Addressing test generation challenges for configurable processor verification
- M. Rimon
- Yossi Lichtenstein
- et al.
- 2006
- HLDVT 2006
Constraint-based random stimuli generation for hardware verification
- Yehuda Naveli
- Michal Rimon
- et al.
- 2006
- AAAI/IAAI 2006
Constraint-based random stimuli generation for hardware verification
- Yehuda Naveh
- Michal Rimon
- et al.
- 2007
- AI Magazine
Genesys-Pro: Innovations in test program generation for functional processor verification
- Allon Adir
- Eli Almog
- et al.
- 2004
- IEEE Design and Test of Computers